`timescale 1ns / 1ps

module display_driver(
	clk_i,
	display_en,
	display_num,
	display_extra
	);
	
	wire clk_1khz;
	
	divider_1khz DIVIDER(
		clk_i,
		clk_1khz
	);
	
	display_half_driver HIGHDIGITS();
	display_low_driver LOWDIGITS();
endmodule
